Opening Up...
Hi, my name is
Final Year MVLSI Student
I am a final-year M.Tech student in Microelectronics and VLSI at IIT Kanpur, with a B.Tech degree from IIT Jammu. My interests lie in both digital and analog circuit design, and I have hands-on experience with industry-standard tools such as Cadence Virtuoso and Icarus Verilog. Alongside my core domain, I am passionate about data structures and competitive programming.
02 / Foundation
Indian Institute of Technology, Kanpur
Grade: 8.00 / 10 CPI
Thesis focused on the design of a ring-based impedance matching network for a Class-AB dual-band power amplifier operating at 2 GHz and 3.5 GHz, achieving over 60% power-added efficiency (PAE) and 15 dB gain at both frequencies.
Indian Institute of Technology, Jammu
Grade: 8.15 / 10 CPI
Final-year project focused on designing a complementary split ring resonator (CSRR)-loaded planar microwave probe for liquid adulteration detection by monitoring shifts in the S-parameter resonance dip.
03 / Build
Designed a mixed-signal IC backend in Verilog to interface with an external controller for start-up sequencing, ensuring proper initialization of analog modules (op-amp, ring oscillator, temperature sensor, and ADC). Implemented and simulated an FSM with serial communication, moving average filtering, and adaptive bias/clock control.
Design, layout and characterization on Cadence Virtuoso and verified with DRC, LVS and PEX checks. Characterized propagation delays for input transitions of 10 ps and 100 ps under output capacitances of 5 fF and 50 fF.
Designed a Single Stage differential amplifier with DC Loop Gain of 34.27 dB, CMRR of 65.46 dB and 3-dB Bandwidth of 83.11 kHz at 300 K using gpdk 180 nm library on Cadence Virtuoso with a load capacitance of 10 pF.
Simulated an FDSOI MOSFET in the TCAD environment for a gate length (LG) of 50 nm, silicon layer thickness (TSi) of 10 nm, and a 3 nm thick gate oxide (TOX) for a nominal supply voltage (VDD) = 1 V. Used SiO2 for the gate oxide material.
Implemented a two-stage op-amp with differential input and single-ended output using NMOS input pairs. Achieved closed loop 3dB bandwidth of 32.017 MHz, DC loop gain of 60.46 dB, phase margin of 66.03◦ all at 300 K, with the load capacitance of 2 pF.
Implemented half and full adders as behaviorally described building blocks for unsigned 8-bit multiply operation. Implemented the design in Verilog and tested functionality with testbench using Icarus Verilog.
This work implements a threshold voltage-based BSIM4 model in Verilog-A using IC-CAP/ADS. The model captures key MOSFET characteristics and higher-order effects, and is validated through standard simulation tests.
Developed a synchronous FIFO in Verilog with 8×16-bit storage, featuring control inputs (write enable, read enable, reset) and outputs for data, full, and empty status. Implemented read/write pointer management and status flag logic to ensure reliable data transfer while preventing overflow and underflow.
MIPS 32 bit RISC-V processor implementation. 5-stage pipeline (Fetch, Decode, Execute, Memory, Writeback) using gate-level, dataflow, and behavioral modeling.
04 / Research
This paper presents a graphical method for designing a distributed series matching network (DSMN). Unlike conventional Smith Chart techniques for single-frequency matching, the proposed approach enables broadband impedance matching through iterative reactance cancellation and impedance rotation. The method is validated using a 6 W broadband GaN HEMT power amplifier operating over 2.1–2.7 GHz (25% fractional bandwidth).
This work presents a high-efficiency dual-band GaN power amplifier with a novel impedance matching network enabling simultaneous matching at 0.85 GHz and 3.5 GHz (frequency ratio of 4.1). A PA using CGH40025F GaN HEMT achieves saturated output powers of 43.2 dBm and 41.2 dBm, with drain efficiency exceeding 60% at both frequencies.
This paper presents an ultra-wideband (UWB) 4-element MIMO antenna with triple band-notched characteristics. The antenna achieves a 143% impedance bandwidth (2–12 GHz), an average gain of 5.3 dBi, and band rejection at 3.55, 5.65, and 8.21 GHz using split ring and complementary split ring resonators.
This work presents compact CSRR-loaded planar microwave probes for liquid adulteration detection. The proposed two-port and single-port sensors can be directly immersed in liquid samples, offering high sensitivity and the ability to distinguish materials with similar dielectric constants.
05 / Bench & Lab
06 / Say hello
Interested in collaborating, discussing engineering, or just connecting? Feel free to reach out via email or connect with me on LinkedIn and Instagram.
